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MYSON TECHNOLOGY
FEATURES
* * * * * Horizontal sync input may be up to 120 KHz. Acceptable wide-range pixel clock up to 96MHz from XIN pin. Full-screen display consists of 15 (rows) by 30 (columns) characters. 12 x 18 dot matrix per character. Total of 256 characters and graphic fonts including 248 mask ROM fonts and 8 programmable RAM fonts. 8 color selection maximum per display character. Double character height and/or width control. Programmable positioning for display screen center. Bordering, shadowing and blinking effect. Programmable vertical character height (18 to 71 lines) control. Row to row spacing register to manipulate the constant display height. 4 programmable background windows with multilevel operation. Software clears for display frame. Half tone and fast blanking output. 8-channel/8-bit PWM D/A converter output. Compatible with SPI bus or I2C interface with address 7AH (slave address is mask option). 16 or 24-pin PDIP/SOP package.
MTV118
On-Screen-Display for LCD Monitor
GENERAL DESCRIPTION
MTV118 is designed for LCD monitor applications to display the built-in characters or fonts onto an LCD monitor screen. The display operates by transferring data and control information from the micro controller to the RAM through a serial data interface. It can execute full screen displays automatically and specific functions such as character bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and windowing effect. Moreover, MTV118 also provides 8 PWM DAC channels with 8-bit resolution and a PWM clock output for external digital-to-analog control.
* * * * * * * * * * * *
BLOCK DIAGRAM
SSB 8 DATA SCK DATA 8 VDD
SERIAL DATA INTERFACE
9 ROW, COL ACK CWS CHS
DISPLAY & ROW CONTROL REGISTERS
LUMAR LUMAG LUMAB BLINK 8 CRADDR
VSS
SDA DATA ARWDB HDREN VDREN NROW 8 5 5 9 9 5 5 RCADDR DADDR FONTADDR WINADDR PWMADDR
VDDA
ADDRESS BUS ADMINISTRATOR
LPN CWS VCLKS
CHARACTER ROM USER FONT RAM LUMINANCE & BORDGER GENERATOR
LUMA VSSA BORDER
VFLB VSP CH 7 CHS VERTD 8
VERTICAL DISPLAY CONTROL
HORIZONTAL DISPLAY CONTROL CLOCK GENERATOR
5 LPN NROW VDREN
DATA 8 8 VERTD 8 HORD 7 CH
WINDOWS & FRAME CONTROL
WR WG WB FBKGC BLANK
BSEN SHADOW OSDENB HSP VSP
HFLB HSP NC XIN PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 HORD 8
ARWDB HDREN LUMAR LUMAG LUMAB BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
VCLKX
COLOR ENCODER
PWM D/A CONVERTER
8 DATA
POWER ON RESET
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. 1/15 MTV118 Revision 2.0 01/01/1999
MYSON TECHNOLOGY
1.0 PIN CONNECTION
VSS XIN NC VDD HFLB SSB SDA SCK
1 2 3 4 5 6 7 8 16 15 14 13
MTV118
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD
VSS XIN NC VDD HFLB SSB SDA SCK PWM0 PWM1 PWM2 PWM3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6 PWM5 PWM4
MTV118
12 11 10 9
MTV118N24
18 17 16 15 14 13
2.0 PIN DESCRIPTIONS
Name VSS XIN NC VDD I/O I I Pin # N16 1 2 3 4 N24 1 2 3 4 Ground. This ground pin is used for internal circuitry. Pixel Clock Input. This is a clock input pin. MTV118 is driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB. No connection. Power supply. Positive 5 V DC supply for internal circuitry. A 0.1uF decoupling capacitor should be connected across VDD and VSS. Horizontal Input. This pin is used to input the horizontal synchronizing signal. It is a leading edge trigger and has an internal pullup resistor. Serial Interface Enabler. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial Data Input. The external data transfers through this pin to internal display registers and control registers. It has an internal pull-up resistor. Serial Clock Input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Open-Drain PWM D/A Converter 0. The output pulse width is programmable by the register of row 15, column 19. Open-Drain PWM D/A Converter 1. The output pulse width is programmable by the register of row 15, column 20. Open-Drain PWM D/A Converter 2. The output pulse width is programmable by the register of row 15, column 21. Descriptions
HFLB
I
5
5
SSB
I
6
6
SDA
I
7
7
SCK PWM0 PWM1 PWM2
I O O O
8 -
8 9 10 11
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Pin # Name PWM3 PWM4 PWM5 PWM6 PWM7 I/O O O O O O N16 N24 12 13 14 15 16 Descriptions
MTV118
Open-Drain PWM D/A Converter 3. The output pulse width is programmable by the register of row 15, column 22. Open-Drain PWM D/A Converter 4. The output pulse width is programmable by the register of row 15, column 23. Open-Drain PWM D/A Converter 5. The output pulse width is programmable by the register of row 15, column 24. Open-Drain PWM D/A Converter 6. The output pulse width is programmable by the register of row 15, column 25. Open-Drain PWM D/A Converter 7. The output pulse width is programmable by the register of row 15, column 26. Power Supply. Positive 5 V DC supply for internal circuitry and a 0.1uF decoupling capacitor should be connected across VDD and VSS. Vertical Input. This pin is used to input the vertical synchronizing signal. It is triggered by lead and has an internal pull-up resistor. Half Tone Output / PWM Clock Output. This is a multiplexed pin selected by the PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect. Fast Blanking Output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue Color Output. This is a blue color video signal output. Green Color Output. This is a green color video signal output. Red Color Output. This is a red color video signal output. Ground. This ground pin is used for internal circuitry.
VDD
-
9
17
VFLB
I
10
18
HTONE / PWMCK
O
11
19
FBKG BOUT GOUT ROUT VSS
O O O O -
12 13 14 15 16
20 21 22 23 24
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
The serial data interface receives data transmitted from an external controller. There are 2 types of bus which can be accessed through the serial data interface: SPI bus and I2C bus. 3.1.1 SPI Bus When the SSB pin is pulled to a HIGH or LOW level, the SPI bus operation is selected. A valid transmission should start from pulling SSB to LOW level, enabling the MTV118 receiving mode and retaining the LOW level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1 on page 4. There are 3 transmission formats as shown below: Format (a) R - C - D R - C - D R - C - D Format (b) R - C - D C - D C - D C - D Format (c) R - C - D D D D D D R=row address, C=column address, D=display data
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SSB
MTV118
SCK
SDA
MS B
first byte last byte
LSB
FIGURE 1. Data Transmission Protocol (SPI) 3.1.2 I2C Bus I2C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin from writing the slave address 7AH, which is mask option, to MTV118. The protocol is shown in Figure 2 on page 4..
SCK
SDA
START
B7
B6
first byte
B0
ACK
B7
B0
ACK STOP
@@@@ @ second byte last byte
FIGURE 2. Data Transmission Protocol (I2C) There are 3 transmission formats as shown below: Format (a) S - R - C - D R - C - D R - C - D Format (b) S - R - C - D C - D C - D C - D Format (c) S - R - C - D D D D D D S=slave address, R=row address, C=column address, D=display data Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and display data (D). Format (a) is suitable for updating small amounts of data which will be allocated with different row and column addresses. Format (b) is recommended for updating data that has the same row address but a different column address. Massive data updating or full screen data changes should be done in format (c) to increase transmission efficiency. The row and column addresses will be incremented automatically when format (c) is applied. Furthermore, the undefined locations in display or font RAM should be filled with dummy data. There are 3 types of data which should be accessed through the serial data interface: address bytes of display registers, attribute bytes of display registers and user font RAM data. The protocol is the same for all except bits 5 and 6 of the row addresses. The MSB(b7) is used to distinguish row and column addresses when transferring data from an external controller. Bit 6 of the row address is used to distinguish display registers and user font RAM data and bit6 of the column address is used to differentiate the column address for formats (a), (b) and (c), respectively. Bit 5 of the row address for display registers is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to "1". The configuration of transmission formats is shown in Table 1 on page 5.
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TABLE 1. Configuration of Transmission Formats Address Address Bytes of Display Reg. Attribute Bytes of Display Reg. User Fonts RAM Row Columnab Columnc Row Columnab Columnc Row Columnab Columnc b7 1 0 0 1 0 0 1 0 0 b6 0 0 1 0 0 1 1 0 1 b5 0 x x 1 x x x C5 C5 b4 x C4 C4 x C4 C4 x C4 C4 b3 R3 C3 C3 R3 C3 C3 x C3 C3 b2 R2 C2 C2 R2 C2 C2 R2 C2 C2 b1 R1 C1 C1 R1 C1 C1 R1 C1 C1
MTV118
b0 R0 C0 C0 R0 C0 C0 R0 C0 C0
Format a,b,c a,b c a,b,c a,b c a,b,c a,b c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure 3 on page 5.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X format (c)
ROW
0, 0
format (b) 0, 0
0, 1
X, X
DAc
FIGURE 3. Transmission State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of internal registers or user font RAM during external data write-in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic incrementation to the address bus when external writing occurs using format (c).
3.3 Vertical Display Control
The vertical display control can generate different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of a double character height bit(CHS) and a vertical display height control register(CH6-CH0).The algorithms of a repeating character line display are shown in Tables 2 and 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
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X, X
COLc
X X,
1 0,
COLab
1, X
DAab
MYSON TECHNOLOGY
MTV118
The vertical display center for a full-screen display may be figured out according to the information of the vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB is calculated using the following equation: Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = 1 horizontal line display time TABLE 2. Repeat Line Weight of Character CH6-CH0 CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4=1 CH3=1 CH2=1 CH1=1 CH0=1 TABLE 3. Repeat Line Number of Character Repeater Line Weight +1 +2 +4 +8 +16 +17 Repeat Line # 0 v 1 v v v 2 v v v 3 v v v 4 v v v 5 v v v 6 v v v 7 v v v 8 v v v 9 v v v 10 v v v 11 v v v 12 v v v 13 v v v 14 v v v 15 v v v 16 v v 17 Repeat Line Weight +18*3 +18*2 +18 +16 +8 +4 +2 +1
+18 v v v v v v v v v v v v v v v v v v Note: "v" means the nth line in the character would be repeated once, while "-" means the nth line in the character would not be repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for a horizontal display based on double character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line includes 360 dots for 30 display characters and the remaining dots for a blank region. The horizontal delay starting from the HFLB leading edge is calculated using the following equation: Horizontal delay time = ( HORD * 6 + 49) * P Where P = 1 XIN pixel display time
3.5 Display & Row Control Registers
The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between row 0/column 0 and row 14/column 29 as shown in Figure 4. Each display register has its corresponding character address on the address byte, and 1 blink bit and its corresponding color bits on attribute bytes. The row control register is allocated at column 30 for row 0 to row 14; it is used to set character size for each respective row. If the double width character (CWS) is cho6/15 MTV118 Revision 2.0 01/01/1999
MYSON TECHNOLOGY
MTV118
sen, only even column characters may be displayed on-screen and the odd column characters will be hidden. ROW # 0 1 COLUMN # 01 28 29 30 31
DISPLAY REGISTERS
ROW CTRL RESERVED REG
13 14 COLUMN# 89
ROW 15
0 WINDOW1
23
11 12 18 19 26 FRAME CRTL PWM D/A WINDOW2 WINDOW3 WINDOW4 REG CRTL REG FIGURE 4. Memory map
56
3.5.1 Register Descriptions 1. (i) Display Register, (Row 0 - 14, Column 0 - 29) ADDRESS BYTE b7 b6 b5 MSB
b4 b3 CRADDR
b2
b1
b0 LSB
CRADDR - Defines ROM character and user-programmable fonts address. (a) 0 ~ 247 248 built-in characters and graphic symbols (b) 248 ~ 255 8 user-programmable fonts ATTRIBUTE BYTE b7 b6 b5 -
b4 -
b3 BLINK
b2 R1
b1 G1
b0 B1
BLINK - Enables blinking effect when this bit is set to " 1 ". The blinking is alternated per 32 vertical frames. R1, G1, B1 - These bits are used to specify its relative address character color 1. 2. Row Control Registers, (Row 0 - 14) COLN 30 b7 b6 b5 b4 R2 b3 G2 b2 B2 b1 CHS b0 CWS
R2, G2, B2 - These bits are used to specify its relative row character color 2. While the corresponding CCS bit is set to 1, color 2 should be chosen. CHS - Defines double height character to the respective row. CWS - Defines double width character to the respective row.
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3.6 User Font RAM
MTV118
The user font RAM has 288 locations which are allocated between row 0/column 0 and row 7/column 35 to specify 8 user-programmable fonts, as shown in Figure 5. Each programmable font consists of a 12x18 dot matrix. Each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as shown in figure 6. That is, the dot matrix data of each font is stored in 36-byte registers. For example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35, etc. ROW # 0 0 1 1 COLUMN # 34 35
36
63
USER FONT RAM
RESERVED
6 7 FIGURE 5. User Font RAM Memory Map
Nth byte leftmost dot of font (N+1)th byte rightmost dot of font
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
12 bits for 1-row data of font dot matrix N=even number
Dummy bits
FIGURE 6. Data Format of Font Dot Matrix
3.7 Character ROM
The character ROM contains 248 built-in characters and symbols from addresses 0 to 247. Each character and symbol consists of a 12x18 dot matrix. The detail pattern structures for each character and symbol are shown in 10.0"CHARACTER AND SYMBOL PATTERN" on page 15.
3.8 Luminance & Border Generator
There are 2 shift registers included in the design which can shift out of luminance and border dots to the color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on 4 sides. For shadowing effect, the character is enveloped with blackedge on right and bottom sides only.
3.9 Window and Frame Control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in Figure 4. Window 1 has the highest priority and window 4 has the least, when 2 windows are overlapping. More detailed information is described as follows:
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1. Window control registers: ROW 15 Column 0,3,6,OR 9 Column 1,4,7,OR 10 Column 2,5,8,OR 11 b7 MSB b7 MSB b7 MSB b6 b5 b4 COL END ADDR b6 b5 ROW START ADDR b4 LSB b6 b5 b4 COL START ADDR b3 MSB b3 LSB b3 LSB b2 WEN b2 R b1 CCS b1 G
MTV118
b2 b1 ROW END ADDR
b0 LSB b0 b0 B
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the start address is greater than the end address, the window will be disabled. WEN - Enables the window display. CCS - When a window is overlapping with the character, character color 2 should be chosen while this bit is set to 1. Color 1 is selected otherwise. R, G, B - Specifies the color of the relative background window. 2. Frame control registers: ROW 15 b7 Column 12 MSB b6 b5 b4 b3 VERTD b2 b1 b0 LSB
VERTD - Specifies the starting position for vertical display. The total steps are 256, and the increment of each step is 4 horizontal display lines. The initial value is 4 after power-up. b7 Column 13 MSB b6 b5 b4 b3 HORD b2 b1 b0 LSB
HORD - Defines the starting position for horizontal display. The total steps are 256 and the increment of each step is 6 dots. The initial value is 15 after power-up. Column 14 b7 b6 CH6 b5 CH5 b4 CH4 b3 CH3 b2 CH2 b1 CH1 b0 CH0
CH6-CH0 - Defines the character vertical height, which is programmable from 18 to 71 lines. The character vertical height is at least 18 lines if the contents of CH6-CH0 are less than 18. For example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. If the contents of CH4-CH0 are greater than or equal to 18, it will be regarded as equal to 17. See Tables 2 and 3 for a detailed description of this operation. Column 15 b7 b6 b5 b4 b3 Reserved b2 b1 b0
This byte is reserved for internal testing.
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Column 16 b7 b6 B5 b4 MSB b3 b2 b1 RSPACE b0 LSB
MTV118
RSPACE - Defines the row to row spacing in each unit of the horizontal line. That is, extra RSPACE horizontal lines will be appended below each display row, and the maximum space is 31 lines. The initial value is "0" after power-up. Column 17 b7 OSDEN b6 BSEN b5 SHADOW b4 TRIC b3 BLANK b2 WENCLR b1 RAMCLR b0 FBKGC
OSDEN - Activates the OSD operation when this bit is set to "1". The initial value is" 0" after power-up. BSEN - Enables the bordering and shadowing effect. SHADOW - Activates the shadowing effect if this bit is set, otherwise the bordering is chosen. TRIC - Defines the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is, while OSD is disabled, these 4 pins will drive LOW if this bit is set to "1", otherwise these pins are in high-impedance state. The initial value is "0" after power-up. BLANK - Forces the FBKG pin output to HIGH while this bit is set to "1". WENCLR - Clears all WEN bits of window control registers when this bit is set to "1". The initial value is "0" after power-up. RAMCLR - Clears all ADDRESS bytes of display registers when this bit is set to "1". The initial value is "0" after power-up. FBKGC - Defines the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the display of characters or windows, otherwise, it outputs only during the display of characters. Column 18 TEST =0 =1 B7 TEST b6 FBKGP b5 PWMCK b4 DWE b3 HSP b2 VSP b1 PWM1 b0 PWM0
Normal mode. Test mode, not allowed in applications.
FBKGP - Selects the polarity of the output pin FBKG. = 1 Positive polarity FBKG output is selected. = 0 Negative polarity FBKG output is selected. The initial value is "1" after power-up. PWMCK - Selects the output options to the HTONE/PWMCK pin. = 0 ? HTONE option is selected. = 1 ? PWMCK option is selected with 50/50 duty cycle and is synchronous with the input HFLB. The frequency is selected by PWM1, PWM0 as shown in table 4. The initial value is "0" after power-up. DWE - Enables double width. When the bit is set to "1", the display of the OSD menu can change to half resolution for double character width, and then the number of pixels of each line should be even. HSP = 1 Accepts positive polarity Hsync input.
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= 0 Accepts negative polarity Hsync input. VSP = 1 Accepts positive polarity Vsync input. = 0 Accepts negative polarity Vsync input.
MTV118
PWM1, PWM0 - Selects the PWMCK output frequency. = (0, 0) XIN frequency /8 = (0, 1) XIN frequency /4 = (1, 0) XIN frequency /2 = (1, 1) XIN frequency /1 The initial value is 0, 0 after power-up. Notes : When XIN is not present, don't write data in any address. If data is written in any address, a malfunction may occur. TABLE 4. PWMCK Frequency and PWMDA Sampling Rate (PWM1, PWM0) ( 0, 0 ) ( 0, 1 ) ( 1, 0 ) ( 1 ,1 ) PWMCK Freq. XIN frequency /8 XIN frequency /4 XIN frequency /2 XIN frequency /1 PWMDA sampling rate XIN frequency /(8 * 256) XIN frequency /(4 * 256) XIN frequency /(2 * 256) XIN frequency /(1 * 256)
3.10 PWM D/A Converter
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). The PWM D/A converter output pulse width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. The sampling rate is selected by PWM1, PWM0 as shown in table 4. In applications, all open-drain output pins should be pulled up by external resistors to supply voltage (5V to 9V) for the desired output range. ROW 15 b7 Column 19 | Column 26 MSB b6 b5 b4 b3 PWMDA0 | PWMDA7 b2 b1 b0
LSB
PWMDA0 - PWMDA7 - Defines the output pulse width of pins PWM0 to PWM7.
3.11 Color Encoder
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD,VDDA) Ground Voltage Storage Temperature Ambient Operating Temperature -0.3 to +7 V -0.3 to VDD+0.3 V -65 to +150 oC 0 to +70 oC
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5.0 OPERATING CONDITIONS
DC Supply Voltage(VDD,VDDA) Operating Temperature +4.75 to +5.25 V 0 to +70 oC
MTV118
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol VIH VIL VOH VOL Parameter Input High Voltage Conditions(Notes) Min. 0.7 * VDD Max. VDD+0.3 0.3 * VDD ( 0.2 * VDD for SSB pin ) 0.5 Unit V
Input Low Voltage Output High Voltage Output Low Voltage
IOH -24 mA IOL 24 mA (For all OD pins, pulled up by external 5 to 9V power supply) 5 mA IDOL ( For all OD pins ) Vin = VDD, Iload = 0uAl Pixel rate=96MHz Iload = 0uA
VSS-0.3 VDD-0.8 -
V V V
VODH VODL ISB ICC
Open Drain Output High Voltage Open Drain Output Low Voltage Standby Current Operating Current
5
9
V
-
0.5 12 20
V mA mA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol fHFLB Tr Tf tBCSU tBCH tDCSU tDCH tSCKH tSCKL tSU:STA tHD:STA tSU:STO Output rise time Output fall time SSB to SCK set-up time SSB to SCK hold time SDA to SCK set-up time SDA to SCK hold time SCK HIGH time SCK LOW time START condition set-up time START condition hold time STOP condition set-up time Parameter HFLB input frequency Min. 15 200 100 200 100 500 500 500 500 500 Typ. Max. 120 5 5 Unit KHz ns ns ns ns ns ns ns ns ns ns ns
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Symbol tHD:STO tSETUP tHOLD tpd PIXin Parameter STOP condition hold time HFLB delay to rising edge of pixel clock minimum pulse width of HFLB propagation delay of output to pixel clock pixel clock input 6 Min. 500 2 25 Typ. -
MTV118
Max. 6 10 96 Unit ns ns ns ns MHz
8.0 TIMING DIAGRAMS
tSCKH
SCK
tSCKL
SSB
tBCSU tBCH
SDA
tDCSU tDCH
FIGURE 7. Data Interface Timing (SPI)
tSCKH
SCK
tSU:STA tSCKL tHD:STO
SDA
tHD:STA tDCSU tDCH tSU:STO
FIGURE 8. Data Interface Timing (I 2C)
PlXin R,G,B, FBKG HTONE tpd tpd:: Propagation Delay to R,G,B, FBKG
and HTONE outputs
HFLB
t SETUP t HOLD
FIGURE 9. Output and HFLB Timing to Pixel Clock
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9.0 PACKAGE DIMENSION
9.1 16 PDIP 300Mil
Unit:Mil
MTV118
312 +/-12 55 +/-20 R40 250 +/-4
R10Max (4X ) 90 +/-20 350 +/-20
75 +/-20 90 +/-20 750 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5
115 Min 100Ty p 18 +/2Typ 60 +/5Typ 15 Min
9.2 24 PDIP 300Mil
Unit: Mil
R10Max (4X)
312+/-12
80+/-20
350+/-20 250+/-4
R40
55+/-20
930+/-10 1245+/-10 15Max 7Ty p 35+/-5
10 65+/-4 65+/-4
115Min
15Min. 100Ty p 18+/2Typ 60+/5Typ
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9.3 16-pin SOP 300Mil
Unit: Mil
MTV118
0.406 +/-0.013 0.295 +/-0.004
0.406 +/-0.008 (4x)
0.015x45o
7o(4x)
0.091
0.098 +/-0.006
0.016 +/-0.004
0.050
0.028 +0.022 /-0.013
9.4 24-pin SOP 300Mil
15.0mm /+0.4 -0.1 24 13 1.85mm/+0.4 -0.15
7.9mm+/-0.4 6.9mm 5.3mm +0.3/-0.1
0.1mm +0.2/-0.05
0.5mm+/-0.2
1 0.45mm +/-0.1 1.27mm
12
0.2mm +0.1/-0.05
10.0 CHARACTER AND SYMBOL PATTERN
Please see the attachment.
Myson Technology, Inc. http://www.myson.com.tw Myson Technology USA, Inc. http://www.myson.com No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002 Tel:408-252-8788 FAX: 408-252-8789 Sales@myson.com
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FEATURES
* * * * * Horizontal sync input may be up to 120 KHz. Acceptable wide-range pixel clock up to 96MHz from XIN pin. Full-screen display consists of 15 (rows) by 30 (columns) characters. 12 x 18 dot matrix per character. Total of 256 characters and graphic fonts including 248 mask ROM fonts and 8 programmable RAM fonts. 8 color selection maximum per display character. Double character height and/or width control. Programmable positioning for display screen center. Bordering, shadowing and blinking effect. Programmable vertical character height (18 to 71 lines) control. Row to row spacing register to manipulate the constant display height. 4 programmable background windows with multilevel operation. Software clears for display frame. Half tone and fast blanking output. 8-channel/8-bit PWM D/A converter output. Compatible with SPI bus or I2C interface with address 7AH (slave address is mask option). 16 or 24-pin PDIP/SOP package.
MTV118
On-Screen-Display for LCD Monitor
GENERAL DESCRIPTION
MTV118 is designed for LCD monitor applications to display the built-in characters or fonts onto an LCD monitor screen. The display operates by transferring data and control information from the micro controller to the RAM through a serial data interface. It can execute full screen displays automatically and specific functions such as character bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and windowing effect. Moreover, MTV118 also provides 8 PWM DAC channels with 8-bit resolution and a PWM clock output for external digital-to-analog control.
* * * * * * * * * * * *
BLOCK DIAGRAM
SSB 8 DATA SCK DATA 8 VDD
SERIAL DATA INTERFACE
9 ROW, COL ACK CWS CHS
DISPLAY & ROW CONTROL REGISTERS
LUMAR LUMAG LUMAB BLINK 8 CRADDR
VSS
SDA DATA ARWDB HDREN VDREN NROW 8 5 5 9 9 5 5 RCADDR DADDR FONTADDR WINADDR PWMADDR
VDDA
ADDRESS BUS ADMINISTRATOR
LPN CWS VCLKS
CHARACTER ROM USER FONT RAM LUMINANCE & BORDGER GENERATOR
LUMA VSSA BORDER
VFLB VSP CH 7 CHS VERTD 8
VERTICAL DISPLAY CONTROL
HORIZONTAL DISPLAY CONTROL CLOCK GENERATOR
5 LPN NROW VDREN
DATA 8 8 VERTD 8 HORD 7 CH
WINDOWS & FRAME CONTROL
WR WG WB FBKGC BLANK
BSEN SHADOW OSDENB HSP VSP
HFLB HSP NC XIN PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 HORD 8
ARWDB HDREN LUMAR LUMAG LUMAB BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
VCLKX
COLOR ENCODER
PWM D/A CONVERTER
8 DATA
POWER ON RESET
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. 1/15 MTV118 Revision 2.0 01/01/1999
MYSON TECHNOLOGY
1.0 PIN CONNECTION
VSS XIN NC VDD HFLB SSB SDA SCK
1 2 3 4 5 6 7 8 16 15 14 13
MTV118
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD
VSS XIN NC VDD HFLB SSB SDA SCK PWM0 PWM1 PWM2 PWM3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6 PWM5 PWM4
MTV118
12 11 10 9
MTV118N24
18 17 16 15 14 13
2.0 PIN DESCRIPTIONS
Name VSS XIN NC VDD I/O I I Pin # N16 1 2 3 4 N24 1 2 3 4 Ground. This ground pin is used for internal circuitry. Pixel Clock Input. This is a clock input pin. MTV118 is driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB. No connection. Power supply. Positive 5 V DC supply for internal circuitry. A 0.1uF decoupling capacitor should be connected across VDD and VSS. Horizontal Input. This pin is used to input the horizontal synchronizing signal. It is a leading edge trigger and has an internal pullup resistor. Serial Interface Enabler. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial Data Input. The external data transfers through this pin to internal display registers and control registers. It has an internal pull-up resistor. Serial Clock Input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Open-Drain PWM D/A Converter 0. The output pulse width is programmable by the register of row 15, column 19. Open-Drain PWM D/A Converter 1. The output pulse width is programmable by the register of row 15, column 20. Open-Drain PWM D/A Converter 2. The output pulse width is programmable by the register of row 15, column 21. Descriptions
HFLB
I
5
5
SSB
I
6
6
SDA
I
7
7
SCK PWM0 PWM1 PWM2
I O O O
8 -
8 9 10 11
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Pin # Name PWM3 PWM4 PWM5 PWM6 PWM7 I/O O O O O O N16 N24 12 13 14 15 16 Descriptions
MTV118
Open-Drain PWM D/A Converter 3. The output pulse width is programmable by the register of row 15, column 22. Open-Drain PWM D/A Converter 4. The output pulse width is programmable by the register of row 15, column 23. Open-Drain PWM D/A Converter 5. The output pulse width is programmable by the register of row 15, column 24. Open-Drain PWM D/A Converter 6. The output pulse width is programmable by the register of row 15, column 25. Open-Drain PWM D/A Converter 7. The output pulse width is programmable by the register of row 15, column 26. Power Supply. Positive 5 V DC supply for internal circuitry and a 0.1uF decoupling capacitor should be connected across VDD and VSS. Vertical Input. This pin is used to input the vertical synchronizing signal. It is triggered by lead and has an internal pull-up resistor. Half Tone Output / PWM Clock Output. This is a multiplexed pin selected by the PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect. Fast Blanking Output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue Color Output. This is a blue color video signal output. Green Color Output. This is a green color video signal output. Red Color Output. This is a red color video signal output. Ground. This ground pin is used for internal circuitry.
VDD
-
9
17
VFLB
I
10
18
HTONE / PWMCK
O
11
19
FBKG BOUT GOUT ROUT VSS
O O O O -
12 13 14 15 16
20 21 22 23 24
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
The serial data interface receives data transmitted from an external controller. There are 2 types of bus which can be accessed through the serial data interface: SPI bus and I2C bus. 3.1.1 SPI Bus When the SSB pin is pulled to a HIGH or LOW level, the SPI bus operation is selected. A valid transmission should start from pulling SSB to LOW level, enabling the MTV118 receiving mode and retaining the LOW level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1 on page 4. There are 3 transmission formats as shown below: Format (a) R - C - D R - C - D R - C - D Format (b) R - C - D C - D C - D C - D Format (c) R - C - D D D D D D R=row address, C=column address, D=display data
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SSB
MTV118
SCK
SDA
MS B
first byte last byte
LSB
FIGURE 1. Data Transmission Protocol (SPI) 3.1.2 I2C Bus I2C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin from writing the slave address 7AH, which is mask option, to MTV118. The protocol is shown in Figure 2 on page 4..
SCK
SDA
START
B7
B6
first byte
B0
ACK
B7
B0
ACK STOP
@@@@ @ second byte last byte
FIGURE 2. Data Transmission Protocol (I2C) There are 3 transmission formats as shown below: Format (a) S - R - C - D R - C - D R - C - D Format (b) S - R - C - D C - D C - D C - D Format (c) S - R - C - D D D D D D S=slave address, R=row address, C=column address, D=display data Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and display data (D). Format (a) is suitable for updating small amounts of data which will be allocated with different row and column addresses. Format (b) is recommended for updating data that has the same row address but a different column address. Massive data updating or full screen data changes should be done in format (c) to increase transmission efficiency. The row and column addresses will be incremented automatically when format (c) is applied. Furthermore, the undefined locations in display or font RAM should be filled with dummy data. There are 3 types of data which should be accessed through the serial data interface: address bytes of display registers, attribute bytes of display registers and user font RAM data. The protocol is the same for all except bits 5 and 6 of the row addresses. The MSB(b7) is used to distinguish row and column addresses when transferring data from an external controller. Bit 6 of the row address is used to distinguish display registers and user font RAM data and bit6 of the column address is used to differentiate the column address for formats (a), (b) and (c), respectively. Bit 5 of the row address for display registers is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to "1". The configuration of transmission formats is shown in Table 1 on page 5.
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TABLE 1. Configuration of Transmission Formats Address Address Bytes of Display Reg. Attribute Bytes of Display Reg. User Fonts RAM Row Columnab Columnc Row Columnab Columnc Row Columnab Columnc b7 1 0 0 1 0 0 1 0 0 b6 0 0 1 0 0 1 1 0 1 b5 0 x x 1 x x x C5 C5 b4 x C4 C4 x C4 C4 x C4 C4 b3 R3 C3 C3 R3 C3 C3 x C3 C3 b2 R2 C2 C2 R2 C2 C2 R2 C2 C2 b1 R1 C1 C1 R1 C1 C1 R1 C1 C1
MTV118
b0 R0 C0 C0 R0 C0 C0 R0 C0 C0
Format a,b,c a,b c a,b,c a,b c a,b,c a,b c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure 3 on page 5.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X format (c)
ROW
0, 0
format (b) 0, 0
0, 1
X, X
DAc
FIGURE 3. Transmission State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of internal registers or user font RAM during external data write-in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic incrementation to the address bus when external writing occurs using format (c).
3.3 Vertical Display Control
The vertical display control can generate different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of a double character height bit(CHS) and a vertical display height control register(CH6-CH0).The algorithms of a repeating character line display are shown in Tables 2 and 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
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X, X
COLc
X X,
1 0,
COLab
1, X
DAab
MYSON TECHNOLOGY
MTV118
The vertical display center for a full-screen display may be figured out according to the information of the vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB is calculated using the following equation: Vertical delay time = ( VERTD * 4 + 1 ) * H Where H = 1 horizontal line display time TABLE 2. Repeat Line Weight of Character CH6-CH0 CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4=1 CH3=1 CH2=1 CH1=1 CH0=1 TABLE 3. Repeat Line Number of Character Repeater Line Weight +1 +2 +4 +8 +16 +17 Repeat Line # 0 v 1 v v v 2 v v v 3 v v v 4 v v v 5 v v v 6 v v v 7 v v v 8 v v v 9 v v v 10 v v v 11 v v v 12 v v v 13 v v v 14 v v v 15 v v v 16 v v 17 Repeat Line Weight +18*3 +18*2 +18 +16 +8 +4 +2 +1
+18 v v v v v v v v v v v v v v v v v v Note: "v" means the nth line in the character would be repeated once, while "-" means the nth line in the character would not be repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for a horizontal display based on double character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line includes 360 dots for 30 display characters and the remaining dots for a blank region. The horizontal delay starting from the HFLB leading edge is calculated using the following equation: Horizontal delay time = ( HORD * 6 + 49) * P Where P = 1 XIN pixel display time
3.5 Display & Row Control Registers
The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between row 0/column 0 and row 14/column 29 as shown in Figure 4. Each display register has its corresponding character address on the address byte, and 1 blink bit and its corresponding color bits on attribute bytes. The row control register is allocated at column 30 for row 0 to row 14; it is used to set character size for each respective row. If the double width character (CWS) is cho6/15 MTV118 Revision 2.0 01/01/1999
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MTV118
sen, only even column characters may be displayed on-screen and the odd column characters will be hidden. ROW # 0 1 COLUMN # 01 28 29 30 31
DISPLAY REGISTERS
ROW CTRL RESERVED REG
13 14 COLUMN# 89
ROW 15
0 WINDOW1
23
11 12 18 19 26 FRAME CRTL PWM D/A WINDOW2 WINDOW3 WINDOW4 REG CRTL REG FIGURE 4. Memory map
56
3.5.1 Register Descriptions 1. (i) Display Register, (Row 0 - 14, Column 0 - 29) ADDRESS BYTE b7 b6 b5 MSB
b4 b3 CRADDR
b2
b1
b0 LSB
CRADDR - Defines ROM character and user-programmable fonts address. (a) 0 ~ 247 248 built-in characters and graphic symbols (b) 248 ~ 255 8 user-programmable fonts ATTRIBUTE BYTE b7 b6 b5 -
b4 -
b3 BLINK
b2 R1
b1 G1
b0 B1
BLINK - Enables blinking effect when this bit is set to " 1 ". The blinking is alternated per 32 vertical frames. R1, G1, B1 - These bits are used to specify its relative address character color 1. 2. Row Control Registers, (Row 0 - 14) COLN 30 b7 b6 b5 b4 R2 b3 G2 b2 B2 b1 CHS b0 CWS
R2, G2, B2 - These bits are used to specify its relative row character color 2. While the corresponding CCS bit is set to 1, color 2 should be chosen. CHS - Defines double height character to the respective row. CWS - Defines double width character to the respective row.
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3.6 User Font RAM
MTV118
The user font RAM has 288 locations which are allocated between row 0/column 0 and row 7/column 35 to specify 8 user-programmable fonts, as shown in Figure 5. Each programmable font consists of a 12x18 dot matrix. Each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as shown in figure 6. That is, the dot matrix data of each font is stored in 36-byte registers. For example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35, etc. ROW # 0 0 1 1 COLUMN # 34 35
36
63
USER FONT RAM
RESERVED
6 7 FIGURE 5. User Font RAM Memory Map
Nth byte leftmost dot of font (N+1)th byte rightmost dot of font
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
12 bits for 1-row data of font dot matrix N=even number
Dummy bits
FIGURE 6. Data Format of Font Dot Matrix
3.7 Character ROM
The character ROM contains 248 built-in characters and symbols from addresses 0 to 247. Each character and symbol consists of a 12x18 dot matrix. The detail pattern structures for each character and symbol are shown in 10.0"CHARACTER AND SYMBOL PATTERN" on page 15.
3.8 Luminance & Border Generator
There are 2 shift registers included in the design which can shift out of luminance and border dots to the color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on 4 sides. For shadowing effect, the character is enveloped with blackedge on right and bottom sides only.
3.9 Window and Frame Control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in Figure 4. Window 1 has the highest priority and window 4 has the least, when 2 windows are overlapping. More detailed information is described as follows:
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1. Window control registers: ROW 15 Column 0,3,6,OR 9 Column 1,4,7,OR 10 Column 2,5,8,OR 11 b7 MSB b7 MSB b7 MSB b6 b5 b4 COL END ADDR b6 b5 ROW START ADDR b4 LSB b6 b5 b4 COL START ADDR b3 MSB b3 LSB b3 LSB b2 WEN b2 R b1 CCS b1 G
MTV118
b2 b1 ROW END ADDR
b0 LSB b0 b0 B
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the start address is greater than the end address, the window will be disabled. WEN - Enables the window display. CCS - When a window is overlapping with the character, character color 2 should be chosen while this bit is set to 1. Color 1 is selected otherwise. R, G, B - Specifies the color of the relative background window. 2. Frame control registers: ROW 15 b7 Column 12 MSB b6 b5 b4 b3 VERTD b2 b1 b0 LSB
VERTD - Specifies the starting position for vertical display. The total steps are 256, and the increment of each step is 4 horizontal display lines. The initial value is 4 after power-up. b7 Column 13 MSB b6 b5 b4 b3 HORD b2 b1 b0 LSB
HORD - Defines the starting position for horizontal display. The total steps are 256 and the increment of each step is 6 dots. The initial value is 15 after power-up. Column 14 b7 b6 CH6 b5 CH5 b4 CH4 b3 CH3 b2 CH2 b1 CH1 b0 CH0
CH6-CH0 - Defines the character vertical height, which is programmable from 18 to 71 lines. The character vertical height is at least 18 lines if the contents of CH6-CH0 are less than 18. For example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. If the contents of CH4-CH0 are greater than or equal to 18, it will be regarded as equal to 17. See Tables 2 and 3 for a detailed description of this operation. Column 15 b7 b6 b5 b4 b3 Reserved b2 b1 b0
This byte is reserved for internal testing.
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Column 16 b7 b6 B5 b4 MSB b3 b2 b1 RSPACE b0 LSB
MTV118
RSPACE - Defines the row to row spacing in each unit of the horizontal line. That is, extra RSPACE horizontal lines will be appended below each display row, and the maximum space is 31 lines. The initial value is "0" after power-up. Column 17 b7 OSDEN b6 BSEN b5 SHADOW b4 TRIC b3 BLANK b2 WENCLR b1 RAMCLR b0 FBKGC
OSDEN - Activates the OSD operation when this bit is set to "1". The initial value is" 0" after power-up. BSEN - Enables the bordering and shadowing effect. SHADOW - Activates the shadowing effect if this bit is set, otherwise the bordering is chosen. TRIC - Defines the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is, while OSD is disabled, these 4 pins will drive LOW if this bit is set to "1", otherwise these pins are in high-impedance state. The initial value is "0" after power-up. BLANK - Forces the FBKG pin output to HIGH while this bit is set to "1". WENCLR - Clears all WEN bits of window control registers when this bit is set to "1". The initial value is "0" after power-up. RAMCLR - Clears all ADDRESS bytes of display registers when this bit is set to "1". The initial value is "0" after power-up. FBKGC - Defines the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the display of characters or windows, otherwise, it outputs only during the display of characters. Column 18 TEST =0 =1 B7 TEST b6 FBKGP b5 PWMCK b4 DWE b3 HSP b2 VSP b1 PWM1 b0 PWM0
Normal mode. Test mode, not allowed in applications.
FBKGP - Selects the polarity of the output pin FBKG. = 1 Positive polarity FBKG output is selected. = 0 Negative polarity FBKG output is selected. The initial value is "1" after power-up. PWMCK - Selects the output options to the HTONE/PWMCK pin. = 0 ? HTONE option is selected. = 1 ? PWMCK option is selected with 50/50 duty cycle and is synchronous with the input HFLB. The frequency is selected by PWM1, PWM0 as shown in table 4. The initial value is "0" after power-up. DWE - Enables double width. When the bit is set to "1", the display of the OSD menu can change to half resolution for double character width, and then the number of pixels of each line should be even. HSP = 1 Accepts positive polarity Hsync input.
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= 0 Accepts negative polarity Hsync input. VSP = 1 Accepts positive polarity Vsync input. = 0 Accepts negative polarity Vsync input.
MTV118
PWM1, PWM0 - Selects the PWMCK output frequency. = (0, 0) XIN frequency /8 = (0, 1) XIN frequency /4 = (1, 0) XIN frequency /2 = (1, 1) XIN frequency /1 The initial value is 0, 0 after power-up. Notes : When XIN is not present, don't write data in any address. If data is written in any address, a malfunction may occur. TABLE 4. PWMCK Frequency and PWMDA Sampling Rate (PWM1, PWM0) ( 0, 0 ) ( 0, 1 ) ( 1, 0 ) ( 1 ,1 ) PWMCK Freq. XIN frequency /8 XIN frequency /4 XIN frequency /2 XIN frequency /1 PWMDA sampling rate XIN frequency /(8 * 256) XIN frequency /(4 * 256) XIN frequency /(2 * 256) XIN frequency /(1 * 256)
3.10 PWM D/A Converter
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). The PWM D/A converter output pulse width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. The sampling rate is selected by PWM1, PWM0 as shown in table 4. In applications, all open-drain output pins should be pulled up by external resistors to supply voltage (5V to 9V) for the desired output range. ROW 15 b7 Column 19 | Column 26 MSB b6 b5 b4 b3 PWMDA0 | PWMDA7 b2 b1 b0
LSB
PWMDA0 - PWMDA7 - Defines the output pulse width of pins PWM0 to PWM7.
3.11 Color Encoder
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD,VDDA) Ground Voltage Storage Temperature Ambient Operating Temperature -0.3 to +7 V -0.3 to VDD+0.3 V -65 to +150 oC 0 to +70 oC
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5.0 OPERATING CONDITIONS
DC Supply Voltage(VDD,VDDA) Operating Temperature +4.75 to +5.25 V 0 to +70 oC
MTV118
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol VIH VIL VOH VOL Parameter Input High Voltage Conditions(Notes) Min. 0.7 * VDD Max. VDD+0.3 0.3 * VDD ( 0.2 * VDD for SSB pin ) 0.5 Unit V
Input Low Voltage Output High Voltage Output Low Voltage
IOH -24 mA IOL 24 mA (For all OD pins, pulled up by external 5 to 9V power supply) 5 mA IDOL ( For all OD pins ) Vin = VDD, Iload = 0uAl Pixel rate=96MHz Iload = 0uA
VSS-0.3 VDD-0.8 -
V V V
VODH VODL ISB ICC
Open Drain Output High Voltage Open Drain Output Low Voltage Standby Current Operating Current
5
9
V
-
0.5 12 20
V mA mA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol fHFLB Tr Tf tBCSU tBCH tDCSU tDCH tSCKH tSCKL tSU:STA tHD:STA tSU:STO Output rise time Output fall time SSB to SCK set-up time SSB to SCK hold time SDA to SCK set-up time SDA to SCK hold time SCK HIGH time SCK LOW time START condition set-up time START condition hold time STOP condition set-up time Parameter HFLB input frequency Min. 15 200 100 200 100 500 500 500 500 500 Typ. Max. 120 5 5 Unit KHz ns ns ns ns ns ns ns ns ns ns ns
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Symbol tHD:STO tSETUP tHOLD tpd PIXin Parameter STOP condition hold time HFLB delay to rising edge of pixel clock minimum pulse width of HFLB propagation delay of output to pixel clock pixel clock input 6 Min. 500 2 25 Typ. -
MTV118
Max. 6 10 96 Unit ns ns ns ns MHz
8.0 TIMING DIAGRAMS
tSCKH
SCK
tSCKL
SSB
tBCSU tBCH
SDA
tDCSU tDCH
FIGURE 7. Data Interface Timing (SPI)
tSCKH
SCK
tSU:STA tSCKL tHD:STO
SDA
tHD:STA tDCSU tDCH tSU:STO
FIGURE 8. Data Interface Timing (I 2C)
PlXin R,G,B, FBKG HTONE tpd tpd:: Propagation Delay to R,G,B, FBKG
and HTONE outputs
HFLB
t SETUP t HOLD
FIGURE 9. Output and HFLB Timing to Pixel Clock
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9.0 PACKAGE DIMENSION
9.1 16 PDIP 300Mil
Unit:Mil
MTV118
312 +/-12 55 +/-20 R40 250 +/-4
R10Max (4X ) 90 +/-20 350 +/-20
75 +/-20 90 +/-20 750 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5
115 Min 100Ty p 18 +/2Typ 60 +/5Typ 15 Min
9.2 24 PDIP 300Mil
Unit: Mil
R10Max (4X)
312+/-12
80+/-20
350+/-20 250+/-4
R40
55+/-20
930+/-10 1245+/-10 15Max 7Ty p 35+/-5
10 65+/-4 65+/-4
115Min
15Min. 100Ty p 18+/2Typ 60+/5Typ
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9.3 16-pin SOP 300Mil
Unit: Mil
MTV118
0.406 +/-0.013 0.295 +/-0.004
0.406 +/-0.008 (4x)
0.015x45o
7o(4x)
0.091
0.098 +/-0.006
0.016 +/-0.004
0.050
0.028 +0.022 /-0.013
9.4 24-pin SOP 300Mil
15.0mm /+0.4 -0.1 24 13 1.85mm/+0.4 -0.15
7.9mm+/-0.4 6.9mm 5.3mm +0.3/-0.1
0.1mm +0.2/-0.05
0.5mm+/-0.2
1 0.45mm +/-0.1 1.27mm
12
0.2mm +0.1/-0.05
10.0 CHARACTER AND SYMBOL PATTERN
Please see the attachment.
Myson Technology, Inc. http://www.myson.com.tw Myson Technology USA, Inc. http://www.myson.com No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002 Tel:408-252-8788 FAX: 408-252-8789 Sales@myson.com
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MTV118 Revision 2.0 01/01/1999

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